Multi-media card (MMC) packages are low-profile integrated circuit (IC) devices, in which memory chips and/or controller chips are incorporated for storing and processing multi-media data such as digital pictures and images. The memory chip and/or controller chip are/is mounted on a chip carrier (e.g. substrate) in the MMC package, so as to allow the chip or chips to be electrically connected to an external device via the chip carrier for operation.
The above MMC package is exemplified as disclosed in U.S. Pat. No. 6,040,622; as shown in FIG. 3A, a substrate 10 made of an organic material, such as a circuit board, is prepared and mounted with an encapsulation wall 11 thereon; the encapsulation wall 11 is formed with a cavity for exposing a predefined chip attach area 12 on the substrate 10, so as to allow at least a chip 13 to be disposed on the exposed chip attach area 12 and received within the cavity. Then, a plastic material 14 is filled into the cavity of the encapsulation wall 11 for encapsulating the chip 13. In another embodiment, as shown in FIG. 3B, firstly, the chip 13 is mounted on the chip attach area 12 of the substrate 10, and then, epoxy resin 15 is applied over the substrate 10 for encapsulating the chip 13; finally, a lidding process is performed to cover a lid 16 over the epoxy resin 15.
The characteristic feature of the above MMC package is to use a plurality of terminals 18 on the substrate 10 as input/output (I/O) ports, as shown in FIG. 3C, wherein the chip 13 is electrically connected to a surface of the substrate 10 by a plurality of bonding wires 17 such as gold wires, and to the terminals 18 formed on an opposing surface of the substrate 10 via conductive vias (not shown) penetrating through the substrate 10, thereby allowing the chip 13 to be electrically coupled to an external device (not shown) by means of the terminals 18 exposed to outside of the package. This structural arrangement can effectively reduce overall thickness of the package, thereby making the package more compact in size. However, the use of an organic substrate as a chip carrier would undesirably increase fabrication costs of the above MMC package. In particular, for reducing the package profile, normally complex arrangement of conductive traces is formed on a small-scale substrate, making fabrication costs for the substrate significantly increased up to around 50% of the package production costs. Moreover, the above MMC package is fabricated by complex processes; for example of batch production of the packages shown in FIG. 3B, die-bonding, wire-bonding, molding, singulation and lidding processes need to be performed, thereby increasing process complexity and costs for package fabrication.
In response to the foregoing high-cost problem, Taiwan Patent Publication No. 484222 discloses a MMC package structure with a lead frame as a chip carrier. As shown in FIG. 4, this package structure utilizes a lead frame 20 having a die pad 21 and a plurality of leads 22 arranged at one side of the die pad 21, each of the leads 22 being composed of an outer lead portion 23, a middle lead portion 24 and an inner lead portion 25, wherein the outer lead portion 23 is connected to the inner lead portion 25 via the middle lead portion 24, and the outer lead portion 23 is positioned with respect to the inner lead portion 25 by a height difference. At least a semiconductor chip 26 such as MMC chip, flash memory chip or controller chip is mounted on the die pad 21 and electrically connected to the inner lead portions 25 by a plurality of bonding wires 27 (e.g. gold wires), wire loops of which bonding wires 27 are not greater in height than the height difference between the inner lead portions 25 and the outer lead portions 23. Then, a molding process is performed; after completing the above die-bonding and wire-bonding processes, the lead frame 20 is placed in a transfer mold (not shown), and a thermosetting resin material such as epoxy resin is injected into the mold; by absorbing heat from the mold, molecules of the resin material are cross-linked and cured to form an encapsulant 28 that encapsulates the chip 26, bonding wires 27, die pad 21 and leads 22, with the outer lead portions 23 being exposed to outside of the encapsulant 28 and acting as I/O ports to be electrically connected to an external device (not shown).
However, the above lead-frame-based package structure still has significant drawbacks; one is deformation of the inner lead portions 25 to form a height difference with respect to the outer lead portions 23, thereby increasing complexity for making the lead frame 20. Moreover, the overall package structure is based on the lead frame 20 that is encapsulated by the encapsulant 28; this would increase material usage of the lead frame 20 and encapsulant 28 as well as fabrication costs of the package structure. During the molding process for forming the encapsulant 28, the outer lead portions 23 intended to be exposed normally can not be firmly clamped by the mold, making the resin material for making the encapsulant 28 may easily flash over and contaminate the outer lead portions 23 acting as I/O ports, thereby degrading quality of electrical connection between the I/O ports and external device; for removing resin flash, an extra deflash process needs to be performed and thus increases fabrication costs. Furthermore, the above package structure after fabrication may retain partial lead portions at the periphery thereof, which degrades the appearance of fabricated products and may also lead to short-circuiting problems that deteriorate reliability of the fabricated products.
Therefore, the problem to be solved herein is to provide a semiconductor package that can reduce fabrication costs, simplify fabrication processes and prevent resin flash, so as to assure reliability and electrical-connection quality of fabricated package products.